The present invention relates generally to the field of memory, and more particularly to a memory module connected to a functional logic, with flexible timing and setup control signals.
Because semiconductor chips, like embedded static random access memory (SRAM) or embedded dynamic random access memory (eDRAM), become more and more complex, related testing processes may be enhanced in their capabilities and flexibility. With increasing speed—i.e., increasing clock frequency—constraints in a timing of signals increase as well. A correct timing of critical signals within such a semiconductor chip becomes paramount to its reliability. Thus, testing methods and timing diagrams for semiconductor devices under test may reflect the critical timing signals in order to guarantee a high reliability of the tested semiconductor chips.
Often, such chips are equipped with built-in self-test (BIST) capabilities. Scan-in chains often deliver the required timing input signals for a device under test. Once a scan-in chain has been filled, a timing of the signals is often fixed. Flexible timing control setup values, such as default values versus maximum frequency values, relaxation times, and so on, may often not be individually altered, assigned, and used during a built-in self-test.